Project38 and Chiplets

Speaker: John Shalf (Slides Here)

Chiplet Interoperability: Universal Test Chip Bring Up Platform and Modular Testing Advancements for ColdADC ASIC Evolution

Speaker: Tarun Prakash, Carl Grace, Bapiraju Vinnakota, Jayaprakash Balachandran (Slides Here)

Organization: Lawrence Berkeley National Laboratory

Abstract: Turned to heterogeneous acceleration to deliver continued performance growth through specialization, chiplets offer a new compelling approach to scaling performance through adding workload-specific processors and massive bandwidth to memory into computing systems. If design and manufacturing challenges are resolved, chiplets can offer a cost effective path for combining die from multiple function-optimized process nodes and even from multiple vendors into a single Application-Specific Integrated Circuit (ASIC). This article explores the opportunities for building and improving the performance of bespoke HPC architectures using open modular “chiplet” building blocks. The hypothesis developed is to use chiplets to extend the functional and physical modularity of modern HPC systems to within the semiconductor package. This planning reduces the complexity and cost of assembling chiplets into an ASIC product and makes it easier to build multiple product variants.

NSA, the DOE Office of Science, and the DOE National Nuclear Security Administration (NNSA) (in this document, these latter two organizations are referred to as “DOE”) recognize the imperative to develop new mechanisms for engagement with the vendor community, particularly on architectural innovations with strategic value to USG HPC. Project 38 is an interagency collaboration between NSA and the DOE, focusing on a set of vendor-agnostic architectural explorations. These explorations are intended to accomplish the following:  Near-term goal: Quantify the performance value and identify the potential costs of specific architectural concepts against a limited, focused set of applications of interest to both the DOE and NSA. Long-term goal: Develop an enduring capability for DOE and NSA to jointly explore architectural innovations and quantify their value.  Project 38 has made significant progress in meeting its near-term goal, and is beginning to share initial exploration results with the wider HPC community, both industry and academia.

Bio: John Shalf is the Department Head for Computer Science at Lawrence Berkeley National Laboratory. He also formerly served as the Deputy Director for Hardware Technology on the US Department of Energy (DOE)-led Exascale Computing Project (ECP) and prior to that was CTO for the National Energy Research Scientific Computing Center (NERSC) at LBNL. He has co-authored over 100 peer-reviewed publications in parallel computing software and HPC technology, including the widely cited report “The Landscape of Parallel Computing Research: A View from Berkeley” (with David Patterson and others). He is also the 2024-2027 distinguished lecturer for the IEEE Electronics Packaging Society. Before joining Berkeley Laboratory, John worked at the National Center for Supercomputing Applications and the Max Planck Institute for Gravitation Physics/Albert Einstein Institute (AEI), where he co-created the Cactus Computational Toolkit.

Supporting High-Performance AI Infrastructure Connectivity with a 3nm Silicon-Proven 24Gbps Universal Chiplet Express (UCIe™) Subsystem

Speaker: Soni Kapoor (Slides Here)

Organization: Alphawave

Abstract: Die-to-die interconnects are the driving force behind the development of disaggregated systems. These interconnects are revolutionizing diverse domains such as data centers, edge computing, artificial intelligence/machine learning (AI/ML), autonomous systems, and high-performance computing (HPC); domains that have typically been addressed monolithically up to the breaking point of operating at the reticle limit. The critical building block that makes this innovation possible is UCIe, Universal Chiplet Interconnect Express. Alphawave Semi has been pioneering D2D technology to fulfill the demand of complex and growing market requirements, which is a key enabler for chiplet connectivity platform tailored for hyperscaler and data-infrastructure applications.

In this demonstration, Alphawave Semi is showcasing their 3nm Silicon-Proven UCIe Interface IP running @24Gbps. Compliant with UCIe Specification Rev 1.1, this UCIe IP has per-lane health monitoring, JTAG, BIST, DFT, KGD test, and debug capabilities from external input or from on-die PRBS generator. Alphawave Semi’s UCIe subsystem is an extremely low power, low latency, flexible and complete D2D solution.

The Open Chiplet Economy – Chapter II (Experience Center)

Speaker: Anu Ramamurthy (Slides Here)

Organization: Open Compute Project

Abstract: Chiplets have rapidly become the accepted way to develop chips at leading-edge nodes.  In theory, they allows designers to drop known-good dies into their designs wherever needed.  However, in practice, designers must have a way to quickly find what they want in a form they can use.  A new chiplet economy is thus necessary.  The Open Compute Project (OCP) has taken the lead in creating that economy.  It started by supporting the Open Domain Specific Project (ODSA) in 2019, and it launched the "open chiplet economy" vision in 2023

Remarkable progress has occurred since the launch.  OCP and JEDEC have used an XML-based schema (developed by OCP) to create the JEP 30 standard.  It allows EDA tools from multiple vendors to handle chiplets.  Recently, 11 organizations showed real products and prototypes based on the standard.  This puts the industry well on the way to defining interoperable chiplets that designers can easily use in applications.  

Current work emphasizes making chiplet-based products easier to develop and market.  The community is creating standard form factors, developing supply chains, and creating an easily accessed marketplace. The idea is to help smaller or peripheral companies create chiplets for AI, IoT, HPC, financial, industrial and process control, and mil/aero markets that have low volumes. We also plan to join with marketing, sales, and business development specialists to identify what is needed to make chiplets financially viable. 

High Performance BoW 2.0 D2D PHY

Speaker: Kevin Donnelly (Slides Here)

Organization: Eliyan

Abstract: Eliyan will demonstrate a test chip featuring its NuLink PHY. Eliyan’s NuLink die-to-die interconnect technology was standardized under OCP as Bunch of Wires (BoW). Eliyan’s test chip was developed on TSMC’s 5nm process and is designed for standard packaging using a 130um bump pitch. All data lanes support bidirectional signaling which can be configured at initialization to be either Transmit or Receive data lanes, as outlined in the BoW 2.0 spec. The total bandwidth supported is over 2Tbps (64 lanes * 32Gbps), yielding a beachfront BW metric of nearly 2Tbps/mm.

Chiplets for Extreme Optical Connectivity

Speaker: Shahab Ardalan (Slides Here)

Organization: Enosemi

Abstract: Monolithic optical chiplets integrate modulator drivers, TIAs, control systems, and photonics on a single silicon die. This degree of integration in an optical chiplet dramatically simplifies the overall multi-chip module and system design and enables ultra-dense optical I/O.

The combination of high-performance devices and compatibility with traditional silicon manufacturing and assembly infrastructure enables ultra high I/O bandwidths and densities in any system and ultimate flexibility: Monolithic optical chiplets can be co-packaged on a laminate substrate with a long-reach SERDES as well as assembled in advanced packages with emerging die-to-die interfaces. Co-integration of optical chiplets not only reduces power consumption by utilizing direct-drive interfaces, but enables low-latency distance-invariant I/O to any system, enabling the next-generation of photonic-enabled systems.

The Enosemi-GUST chiplet has 16 channels including both transmitter and receiver for O-band optical communication fabricated in the GlobalFoundries Fotonix (45SPCLO) platform. The transmitter and receiver show an open 112 Gbps PAM4 eye at a 4.3 pJ/bit energy efficiency, not including the laser. The chiplet is PHY agnostic and can be co-packaged with XSR, LR, PCIe, UCIe, BoW or any other NRZ/PAM-4 PHYs.

Enabling the Open Chiplet Economy: Design Kits, Workflows and Tools for 3D-ICs

Speaker: David Ratchkov (Slides Here)

Organization: Anemoi Software

Abstract: With the increasing importance of chiplets in the landscape of system design, there is burgeoning interest in how these components can be effectively integrated into new systems. The shift in focus has necessitated a migration of many traditional design steps to the preliminary stages of business planning and architectural design. This evolution in design methodology is being driven by innovative workflows, which are bolstered by the latest updates in Design Kits.

This demonstration highlights the array of Design Kits developed at CDX, which includes the Chiplet Design Kit (CDK), Material Design Kit (MDK), Assembly Design Kit (ADK), Chiplet Test Design Kit (CTDK), and Chiplet SI/PI Design Kit (CIDK), along with detailed chiplet descriptions in the CDXML format. The primary objectives of this demonstration are threefold: to define and publish a new chiplet, to facilitate the integration of multiple chiplets into cohesive systems, and to conduct early-stage analytical assessments. 

Robust Die-to-Die Connectivity with UCIe IP

Speaker: Monica Olvera (Slides Here)

Organization: Synopsys

Abstract: See a demo of our UCIe IP showing excellent performance at 24GT/s and a low bit error rate. The IP can operate up to 40GT/s while supporting standard and advanced package technologies. It includes features to ensure die-to-die and die-to-system reliability at the highest levels. The IP has achieved silicon success in multiple foundry processes, and it has been adopted by multiple customers.

Blue Cheetah BlueLynx Chiplet Interconnect IP

Speaker: Bhaskar Acharya (Slides Here)

Organization: Blue Cheetah Analog

Abstract: BlueLynx Is being used in many chiplet based ecosystems developing today to deliver ASICs for very advanced AI, HPC, automotive, commercial products. Many of these products are using OCP Bunch of Wires (BoW) with customizations to enable low-cost packaging use cases. Blue Cheetah will demonstrate how it can deliver the industry's most advanced power/area efficient PHY architecture already used by multiple semiconductor foundries today and implemented across 7 different process nodes, including 5nm and below